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Technology: Has HBM replaced CoWoS as the binding constraint on AI accelerator output?

2026-05-27 · long-form

Executive summary

The question this report answers is whether high-bandwidth memory (HBM) has definitively replaced TSMC's CoWoS advanced packaging as the binding capacity constraint on AI accelerator output, or whether both are still co-binding through 2026. The answer is that both still bind — but the binding order has formally inverted within the last two quarters, and the market is now pricing that inversion as structural rather than cyclical. That last part is where AlphaSteve's read departs from the consensus framing.

The hard observable behind the inversion is the language NVIDIA's own management is using. On the most recent disclosure cycle, Jensen Huang identified memory (HBM) as the primary supply bottleneck and advanced process capacity as secondary T1. That is a re-ordering relative to the 2024–2025 framing, where CoWoS-L was the headline gating constraint on Blackwell ramp. The re-ordering reflects two underlying facts. First, TSMC's CoWoS capacity is on track to nearly quadruple from approximately 35,000 wafers per month at end-2024 to 120,000–130,000 wpm by end-2026 T2. Second, HBM industry capacity is scaling materially less — Samsung is targeting 250,000 wpm by end-2026 (+47% from ~170k) T3; SK Hynix is starting its M15X HBM4 line at just 10,000 wpm with plans to scale "severalfold" through end-2026 T3; and every named HBM supplier is sold out through CY2026 T1.

The market's response over the past 48 hours — Micron crossing $1T market cap Tuesday on a UBS $1,625 Street-high price target explicitly arguing "AI has structurally changed memory market," and SK Hynix joining the trillion-dollar club Wednesday on the same structural-driver thesis — is directionally right on the inversion but underweights the variance around the duration of the constraint. Memory is still a cyclical industry, the second derivative of HBM-specific supply is positive across all three players for the first time this cycle, and SK Hynix's first-quarter 72% operating margin print T1 is the kind of through-cycle anomaly the capital-cycle literature predicts gets competed away — not necessarily in twelve months, but on a horizon the multiple is now ignoring.

House view reconciliation

The current house view position _house-view "AI infrastructure capacity — current" (last updated 2026-05-27 AM) is: "Demand for accelerated-compute capacity remains far ahead of supply at the leading edge. Hyperscaler capex commitments through 2027 are large and visible. The bottleneck has migrated from GPU silicon to HBM, advanced packaging (CoWoS), and power/grid availability." This report extends and sharpens that position with three specific refinements: (i) within the HBM/CoWoS/power triple, the ordering has now formally inverted with HBM moving from co-equal to primary on NVIDIA's own management commentary; (ii) the inversion is structural for the next 12-18 months on the supply-side ramp differential between CoWoS (4x) and HBM (~1.5x); (iii) the cohort psychology pricing the inversion as permanent (UBS $1,625 MU PT; SK Hynix $1T market cap in 24 hours) is where AlphaSteve's variant view differs — the constraint is real but the duration-of-rent framing the cohort is paying for is over-extrapolated. Specific _house-view update: see the "House view changes this run" section below for the proposed update text and the rationale.

The setup

The AI-accelerator value chain has three serially-tight choke points at the leading edge: leading-edge logic fabrication (TSMC N3/N4P/N2), advanced 2.5D packaging (TSMC CoWoS-S and CoWoS-L variants), and high-bandwidth memory (SK Hynix, Samsung, Micron). All three are required to produce a finished AI training accelerator at the level NVIDIA Blackwell or AMD MI300X/MI400 sit. The question of "which is binding" is therefore the question of which one runs out first when demand is added at the margin.

Through 2023–2024, the headline binding constraint was CoWoS — specifically the CoWoS-S variant for Hopper and CoWoS-L for Blackwell. CoWoS-L is required because the Blackwell B200/GB200 generation is effectively a multi-die package that needs the larger-area interposer the L variant provides T3. TSMC's response was a multi-year capacity buildout — the AP6 (Zhunan), AP7 (Chiayi) and AP8 (Tainan) advanced backend facilities — that the company communicated as roughly quadrupling CoWoS capacity by end-2026 from end-2024 levels.

Through 2025–2026, that buildout has begun to deliver. Industry tracker estimates put CoWoS monthly wafer-start capacity at approximately 70,000–80,000 wpm by mid-2026 with the formal ramp to ~127,000–130,000 wpm by year-end T3. While CoWoS was scaling, HBM was scaling more slowly: SK Hynix's per-year HBM3E wafer-equivalent capacity grew by roughly 70–80% YoY 2024→2025 T1; Samsung's HBM line was ramping from a smaller base into NVIDIA qualification on HBM3E 12-Hi only in September 2025 T3; and Micron — entering HBM materially behind the two Korean leaders — moved from HBM3E into HBM4 qualification within the same period T3.

The mechanical result of these two ramp curves crossing is what the past two trading days have priced: HBM has become the tighter of the three serial constraints even as CoWoS is also still binding. The Wednesday morning Asia cohort tape — KOSPI +4.56% to a fresh record close 8,457, SK Hynix +9.9% to join MU in the trillion-dollar-market-cap club after Tuesday's +19.3% MU re-rating T3 — is the cohort psychology operating at the most stretched intensity the kit has tracked. The question for AlphaSteve is whether the framing the cohort is buying into is structural — memory has been permanently re-rated by AI — or cyclical-with-an-elongated-tail.

The analysis

Capacity arithmetic: the binding crossover

The cleanest way to see the constraint inversion is the supply-ratio arithmetic. CoWoS capacity grows roughly 4x from end-2024 to end-2026 T3. HBM industry capacity at the leading edge grows materially less — Samsung's stated target is +47% in HBM-allocated wafers over the same window T3 and SK Hynix's M15X starts at 10k wpm 1b DRAM for HBM4 with planned scaling "severalfold" by end-2026 T3. If we use Morgan Stanley's industry forecast of 1 million CoWoS wafers in 2026 against Samsung's 250k wpm end-state and apply the standard wafer-equivalent translations, the implied AI-accelerator throughput becomes HBM-gated rather than CoWoS-gated for the first time in the cycle.

Constraint End-2024 capacity End-2026 target Multiple Status by mid-2026
TSMC CoWoS (S+L) advanced packaging ~35k wpm ~120-130k wpm ~3.5–4x Still tight; CoWoS-L specifically near 100% util; expansion delivering
SK Hynix HBM (industry leader) ~120k wpm-equivalent ~170k wpm scaling severalfold for HBM4 line ~1.5–2x Sold out CY2026
Samsung HBM ~170k wpm ~250k wpm (+47%) ~1.5x Sold out; HBM4 NVIDIA share ~mid-20%
Micron HBM smaller base, sold out CY2026 Singapore packaging facility from CY2027 smaller absolute add Sold out CY2026 T1

Sources: TSMC CoWoS estimates from TrendForce / Morgan Stanley industry consensus, 2026-Q1, summarised in semi trade press; SK hynix figures from T1 and T3; Samsung from T3; Micron from T2.

The arithmetic point is simple. When two serial constraints expand at different rates, the slower-expanding one becomes the binding constraint at the date the curves cross. The constraint that grows 4x stops being limiting when the constraint that grows 1.5x is required in roughly fixed proportion per finished accelerator (Blackwell typically pairs ~6 HBM stacks per GPU; Rubin generation increases stack count further T3). The cross-over date — somewhere in late Q2 / early Q3 2026 by the supply-tracker consensus — is the moment when the binding constraint moves cleanly from CoWoS to HBM. That moment is approximately now.

The NVIDIA management re-ordering

The clearest single piece of T1 evidence that the inversion is real, and not just a supply-tracker artifact, is the explicit re-ordering of constraints by NVIDIA management. On the Q1 FY27 print disclosure cycle (2026-05-20), Huang named memory (HBM) as the primary bottleneck, with advanced process capacity (which includes CoWoS) as secondary T1. That re-ordering matters not because management commentary is unbiased — management has strategic incentives to point at whichever constraint is most defensible — but because it commits to the framing on the earnings tape. If HBM eases before CoWoS, the management has a credibility problem.

Huang's additional remark that "Nvidia will be constrained throughout the entire life of Vera Rubin" T3 is the second meaningful disclosure. Rubin generation begins shipping in second-half calendar 2026 and runs through 2027–2028; a multi-year-constraint statement from the dominant accelerator OEM is itself evidence that the supply curves the supply-tracker industry models forecast through 2027 are still demand-undershooting.

Where the rent is now sitting

The bottleneck framework predicts that when a constraint binds, the rent migrates to the owner. The visible evidence on the Q1 2026 earnings tape is consistent: SK Hynix Q1 2026 operating margin came in at 72% on revenue of ₩52.6 trillion T1, up roughly 60% QoQ and 198% YoY. Net margin 77%. Operating margins of that magnitude in a historically-cyclical commodity industry — DRAM operating margins have averaged in the 20–35% range through-cycle since the early 2010s, with peak-cycle prints in the 50s — are the textbook signature of a bottleneck owner extracting rent in an extreme demand-supply imbalance.

Two checks against the rent thesis are worth noting. First, the rent at the HBM supplier level is visible in the multiple expansion the cohort has just delivered: MU added $160B+ of market cap Tuesday on UBS's $1,625 Street-high target T3; SK Hynix added ~$100B equivalent Wednesday T3. The market is pricing the rent. Second, the CoWoS rent is harder to see because TSMC reports advanced packaging within its broader 2.5D/3DFabric / N+1 capacity disclosures rather than as a discrete segment; the company's blended Q1 2026 operating margin was 49% T1. That is still a margin level inconsistent with competitive equilibrium, but the delta in operating margin relative to prior cycles is materially smaller than what HBM is now showing — which is exactly what the constraint-inversion model predicts.

The downstream-rent question

The bottleneck framework also predicts that downstream firms whose margins depend on bottleneck capacity get squeezed when rents migrate upstream. The cleanest visible manifestation: NVIDIA's most recent disclosure cycle shows gross margin compression from a peak in late 2024 to the Q1 FY27 print — the company has been absorbing HBM cost inflation as it has moved up the bill-of-materials T1. NVIDIA is the dominant accelerator OEM and has the negotiating leverage to push HBM cost back through to hyperscaler customers eventually, but the timing of that pass-through is the gating factor on the GPU vendor's near-term margin. AMD and the custom-silicon ecosystem (Broadcom, Marvell at hyperscalers' direction) face the same arithmetic with less negotiating leverage T3.

The hyperscaler downstream is where the squeeze ultimately accrues if HBM cost pass-through is incomplete. Aggregate hyperscaler capex of approximately $725B in 2026, up 77% YoY from $410B T3, is being deployed against an accelerator output that is capacity-gated by HBM, not by capex willingness. The capex curve is no longer the constraint; the bottleneck is.

Variant perception

Consensus framing — visible in the UBS $1,625 MU price target argument that "AI has structurally changed memory market" T3 and the cohort multiple expansion of the past 48 hours — is that HBM has been structurally re-rated by AI demand and that memory's historically-cyclical multiple is no longer the right valuation anchor. The structural framing implicitly assumes that the constraint persists long enough to amortize across a memory pricing cycle that classical cyclical-bottom arithmetic would suggest is coming, and that the second derivative of HBM supply remains negative-or-flat for long enough that the cohort multiple is justified.

AlphaSteve's variant perception is more cautious. The constraint is real and the inversion from CoWoS-binding to HBM-binding is happening as the market is pricing it. But three observations push the structural framing toward the cyclical end of the structural-cyclical continuum.

First, the second derivative of HBM industry supply is now positive across all three players simultaneously for the first time in this cycle: Samsung's 50% capacity surge plan T3, SK Hynix's M15X HBM4 line ramp T3, Micron's Singapore packaging facility for CY2027 T2. The textbook capital-cycle dynamic capital-cycle is that when three suppliers are all expanding hard simultaneously into a constraint, the supply response over the next 24–36 months is the part the multiple is most prone to mis-anchoring.

Second, Samsung's HBM3E 12-Hi qualification at NVIDIA in September 2025 T3 is the textbook signal that the entry-of-competition lever is being pulled at this cycle peak. Until late 2024, the HBM market was effectively a duopoly (SK Hynix + Samsung) with SK Hynix as NVIDIA's only qualified supplier for top-end HBM3E. Adding a second qualified vendor at the leading-edge customer is exactly the move that re-rates the future pricing curve toward competitive normalisation, even if the current spot is still binding.

Third, the Vera Rubin commentary cuts both ways. Huang's statement that constraint persists "throughout the entire life of Vera Rubin" is conditional on the demand curve continuing to scale faster than supply curve. If the algorithmic efficiency curve flattens the inference-compute-per-token slope by more than ~50% — a documented risk in the house view _house-view AI-capacity material-risks list — the demand-side mathematics inverts faster than the supply-side. The bottleneck holds only as long as the demand line outruns the supply line, and we have just observed three suppliers simultaneously pivoting capacity hard.

The cleanest 12-24-month falsification test of AlphaSteve's variant view: NVIDIA's CFO commentary on a future quarterly disclosure either (a) re-orders advanced process back to primary and HBM to secondary, or (b) drops the "constrained throughout Vera Rubin" framing — either is evidence the variant is becoming consensus and the multiple is starting to re-rate down. Confirmation of the variant: SK Hynix HBM-allocated operating margins decline materially below the Q1 2026 72% print over the next 2-3 quarters even as revenue continues to grow.

Implications for AlphaSteve

The Wednesday tape is pricing the constraint inversion as structural. AlphaSteve's read is that the inversion is real and the house view's HBM-as-binding framing is now formally correct on the supply-tracker arithmetic and NVIDIA's own management commentary — but the cohort multiple expansion is over-extrapolating duration, and patience-window discipline says hold cash through the resolution. The MRVL/CRM evening prints tonight remain the cleanest single discriminating test for whether cohort psychology can absorb a "merely good" print on a downstream-of-bottleneck name without retracement; a beat-and-fade in MRVL on stretched-cohort tape would mark the first cohort retracement since NVDA's Q1.

  • Portfolio: no action; AI-infrastructure-upstream exposure remains zero on margin-of-safety discipline. Cohort-psychology levels are the most stretched the kit has tracked.
  • Watchlist: SK Hynix (000660.KS), Micron (MU), and Samsung Electronics (005930.KS) all carry the cohort-extension risk. MP Materials thesis pass remains top priority this week — structural drivers decoupled from the Iran trinary and from the HBM cycle.
  • Theses on the workbench: no new thesis from this report; the constraint-inversion is observational and informs framing rather than triggering a position-level expression.
  • Sectors: Information Technology / Semiconductors sub-industry — HBM as primary bottleneck reinforces the sector's "Bottleneck patterns" entry 08-information-technology; the framework section needs no rewrite, the observation extends an existing entry.
  • House view updates: see the "House view changes this run" section. Specific update is to the "AI infrastructure capacity — current" position language, reflecting the constraint-inversion as confirmed-via-NVIDIA-commentary.
  • Daily-scan adjustments: add to the Wednesday daily-scan the explicit observable "any HBM supplier disclosure that indicates capacity is not sold out through 2026" or "any NVIDIA management re-ordering of constraints" — either would falsify the current position and trigger material re-pricing.

Charts / data

Table 1 (above) — Constraint capacity arithmetic 2024 → 2026.

Table 2 — Tier-1 evidence on constraint binding, by source.

Constraint T1 evidence binding mid-2026 Source
CoWoS-L (NVIDIA-specific) NVIDIA ~70% of CoWoS-L allocation; ~60% of total CoWoS; TSMC near 100% utilisation T2; T3
HBM (SK Hynix) "Customer demand for HBM for next three years far exceeds SK Hynix's current supply capacity" T1
HBM (Micron) "HBM3E and HBM4 production capacity sold out" CY2026 T2
HBM ordering by NVIDIA management "Primary supply bottleneck is currently memory (HBM), followed by advanced process capacity" T1; T3
Constraint persistence through Vera Rubin life "Nvidia will be constrained throughout the entire life of Vera Rubin" T3

Sources

See sources-policy for citation discipline applied. Wikipedia banned per policy; not used in this report. T3 citations carry named outlets and dates; load-bearing claims on capacity tonnage and constraint inversion are anchored in T1 (NVDA CFO commentary, SK Hynix PR) or T2 (Morgan Stanley industry analysis, io-fund Micron writeup), with T3 used for industry-tracker context and cohort-tape colour.

House view changes this run

Updating _house-view AI infrastructure capacity — current to formally reflect the constraint inversion. Proposed update text:

Position (as of 2026-05-27 Wednesday long-form): Demand for accelerated-compute capacity remains far ahead of supply at the leading edge. Hyperscaler capex commitments through 2027 are large ($725B 2026 / $1T+ 2027 trajectory) and visible. The binding constraint has now formally inverted from CoWoS-primary / HBM-secondary (the 2024-2025 framing) to HBM-primary / CoWoS-secondary, on the basis of NVIDIA management commentary (Q1 FY27 CFO Commentary; "constrained throughout entire life of Vera Rubin"), the supply-ratio arithmetic (CoWoS ~4x ramp 2024→2026 vs HBM ~1.5x), and three-supplier sold-out-through-2026 disclosure (SK Hynix Q1 2026 PR; Micron Q2 FY26 commentary; Samsung allocation mix). The inversion is real and observed but the duration the market is pricing — through cohort multiple expansion delivering two $1T memory re-ratings in 24 hours on the UBS structural-rerate framing — over-extrapolates the structural-vs-cyclical balance; three-supplier simultaneous capacity expansion, Samsung's NVIDIA HBM3E qualification, and the algorithmic-efficiency demand-side risk all push toward the "elongated cyclical" rather than "permanent structural" end of the framing. Confidence: high on the constraint-inversion observation; medium on the duration question.

The "Material risks" list gets one new entry: "three-supplier simultaneous HBM capacity ramp through end-2026 transitions the market from supply-binding to supply-balanced in late 2027 / 2028 — would re-rate the cohort multiple materially lower from current levels."

Adding entry to the changes log dated 2026-05-27 Wednesday long-form (technology): constraint-inversion observation; supply-arithmetic table; variant perception flagged on duration-of-bottleneck pricing.

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